1. Field of the Invention
The present invention relates to semiconductor packages and fabrication methods thereof, and more particularly, to a semiconductor package and a fabrication method thereof for meeting the miniaturization requirement of electronic products.
2. Description of Related Art
Along with the rapid development of electronic industries and the progress of semiconductor processing technologies, semiconductor chips are integrated with more electronic elements to achieve better electrical performance. Accordingly, the semiconductor chips are provided with more I/O connections. To meet the miniaturization requirement of semiconductor packages, substrates used for carrying the semiconductor chips are required to have a high density of wire bonding pads corresponding to the I/O connections of the semiconductor chips. FIG. 1A shows a conventional semiconductor package 1.
Referring to FIG. 1A, a semiconductor chip 13 is disposed on a substrate 10, and electrode pads 130 of the semiconductor chip 13 are electrically connected to wire bonding pads 102 of the substrate 10 through a plurality of bonding wires 14. Then, an encapsulant 15 is formed on the substrate 10 for encapsulating the semiconductor chip 13 and the bonding wires 14.
However, in order to meet the miniaturization requirement, the space on the substrate 10 around the semiconductor chip must be reduced, thus resulting in a high density of the wire bonding pads 102. Therefore, it becomes difficult to perform a wire bonding process. Further, a short circuit easily occurs between adjacent bonding wires 14.
To overcome the above-described drawbacks, a plurality of switching pads are provided for electrically connecting electrode pads of a semiconductor chip and wire bonding pads of a substrate, as shown in FIGS. 1B and 1B′.
Referring to FIG. 1B, a substrate 10 having an insulating layer 10b and a circuit layer 10a embedded in the insulating layer 10b is provided. The circuit layer 10a has a plurality of switching pads 100, a plurality of first and second wire bonding pads 101, 102′ and a plurality of circuits 103 formed between the switching pads 100 and the first wire bonding pads 101. A semiconductor chip 13 having a plurality of electrode pads 130 is disposed on the substrate 10. A portion of the electrode pads 130 of the semiconductor chip 13 are electrically connected to the switching pads 100 through a plurality of first short bonding wires 14a, and the switching pads 100 are further electrically connected to the first wire bonding pads 101 through a plurality of second short bonding wires 14b. The other portion of the electrode pads 130 of the semiconductor chip 13 are electrically connected to the second wire bonding pads 102′ through a plurality of bonding wires 14. Then, an encapsulant 15 is formed on the substrate 10 for encapsulating the semiconductor chip 13, the first and second short bonding wires 14a, 14b, the bonding wires 14, the switching pads 100, and the first and second wire bonding pads 101, 102′. Thereafter, a plurality of conductive elements 16 such as solder balls are formed on portions of the circuit layer 10a exposed from the insulating layer 10b. 
However, since the second short bonding wires 14b have a certain wire loop, the second short bonding wires 14b easily come into contact with the bonding wires 14 and cause a short circuit.
To overcome the above-described drawback, the wire loop of the bonding wires 14 can be increased, which however increases the overall height of the semiconductor package 1′ and hinders the miniaturization of the semiconductor package 1′.
Further, since the substrate 10 only has the single circuit layer 10a, the wiring space of the substrate 10 is quite limited and not flexible. As such, the circuits 103 can only be formed in a plane instead of in multiple layers.
Therefore, how to overcome the above-described drawbacks has become urgent.